1. Field of the Invention
The present invention refers to a phase-locked loop.
2. Description of the Related Art
The use of transmitters and receivers using phase-locked loops (PLL) based on frequency synthesizers in modern plants of radio frequency telecommunications is generally known. Several critical parameters for the frequency synthesizers used in applications of telecommunications are the switching time, the phase noise and other.
A low phase noise and a high switching speed are obtained with fractional synthesizers. A typical PLL based on a fractional frequency synthesizer at N, with N an integer number, is shown in FIG. 1. Said PLL comprises a crystal oscillator 1 that supplies an oscillation frequency to a reference divider 2 to obtain a reference frequency fr1. The latter is in input to a phase detector (PD) 3 that also has in input a frequency fv1 coming from a fractional divider 4. The signals in output from the phase detector are in input to a charge pump 5 whose output is connected to a filter 6 from which the direct current for driving a voltage controlled oscillator VCO 7 arrives; the frequency fo1 in output from the VCO is in input to the fractional divider 4 capable of switching from a division by N to a division by N+1, with N an integer number. The PLL also comprises an L-bit accumulator 8, with L an integer number, that is increased continuously by a quantity x1 on the reference ratio given by the maximum count m with m=2L; the accumulator 8 acts on the fractional divider 4 like a binary adder at L-bit with status registers having as addends the previous status and x1, with x1=0, 1, 2, . . . m−1. The accumulator 8 permits the scattering of the periods of division by N and N+1 to attenuate the spurious harmonics produced by the divider 4. The frequency fo is divided in x1/m fractions of the reference frequency fr1, that is fo=Nf*fr1 where Nf=N+x1/m with x1=0, 1, 2, . . . m−1; the ratio x/m represents the fractional part of Nf. The divider 4 will divide by N when the accumulator is increasing up to the maximum count m−1 and divide by N+1 when it exceeds the count m−1.
A disadvantage of the above mentioned type of frequency synthesizers lies in the phase ripple present on the output of the phase detector that gives rise to a current Icp1 of the PWM type. If said current is not compensated for, an energy in sideband on the output spectrum of the VCO is produced that is considered the greatest problem for such synthesizers.
One way to compensate for the current Icp1 is carried out by the PLL of FIG. 2. In this case the phase ripple PWM is proportional and synchronized to the contents of the L-bit accumulator 8 and can be used to control the width of the compensation pulse in sideband. The PLL of FIG. 2 comprises, in addition to the elements of the PLL of FIG. 1, a fractional synchronization circuit 11, a fractional charge pump 12 and a digital-analog converter (DAC) 13. The fractional pulses, which are controlled on a constant ratio, have constant width and their height is modulated. The content of the accumulator 8 feeds the DAC 13 and is used to modulate the width of the compensation current Icomp1 generated by the fractional pump 12. The circuit 11 operates at a frequency fixed by the crystal 1, is controlled by the signal fv coming from the main divider 7, and produces the fractional compensation pulse at fixed width that controls the charge pump 12. The pulse amplitude modulation (PAM) signal in output from the pump 12 is adapted to cancel the PWM spurious signals coming from the charge pump 4. Nevertheless in this manner optimum compensation of the current Icp is not obtained, that is, there is not a total cancellation of the spurious signals coming from the charge pump 4.